library verilog;
use verilog.vl_types.all;
entity CORTEXM0INTEGRATION is
    port(
        FCLK            : in     vl_logic;
        SCLK            : in     vl_logic;
        HCLK            : in     vl_logic;
        DCLK            : in     vl_logic;
        PORESETn        : in     vl_logic;
        DBGRESETn       : in     vl_logic;
        HRESETn         : in     vl_logic;
        SWCLKTCK        : in     vl_logic;
        nTRST           : in     vl_logic;
        HADDR           : out    vl_logic_vector(31 downto 0);
        HBURST          : out    vl_logic_vector(2 downto 0);
        HMASTLOCK       : out    vl_logic;
        HPROT           : out    vl_logic_vector(3 downto 0);
        HSIZE           : out    vl_logic_vector(2 downto 0);
        HTRANS          : out    vl_logic_vector(1 downto 0);
        HWDATA          : out    vl_logic_vector(31 downto 0);
        HWRITE          : out    vl_logic;
        HRDATA          : in     vl_logic_vector(31 downto 0);
        HREADY          : in     vl_logic;
        HRESP           : in     vl_logic;
        HMASTER         : out    vl_logic;
        CODENSEQ        : out    vl_logic;
        CODEHINTDE      : out    vl_logic_vector(2 downto 0);
        SPECHTRANS      : out    vl_logic;
        SWDITMS         : in     vl_logic;
        TDI             : in     vl_logic;
        SWDO            : out    vl_logic;
        SWDOEN          : out    vl_logic;
        TDO             : out    vl_logic;
        nTDOEN          : out    vl_logic;
        DBGRESTART      : in     vl_logic;
        DBGRESTARTED    : out    vl_logic;
        EDBGRQ          : in     vl_logic;
        HALTED          : out    vl_logic;
        NMI             : in     vl_logic;
        IRQ             : in     vl_logic_vector(31 downto 0);
        TXEV            : out    vl_logic;
        RXEV            : in     vl_logic;
        LOCKUP          : out    vl_logic;
        SYSRESETREQ     : out    vl_logic;
        STCALIB         : in     vl_logic_vector(25 downto 0);
        STCLKEN         : in     vl_logic;
        IRQLATENCY      : in     vl_logic_vector(7 downto 0);
        ECOREVNUM       : in     vl_logic_vector(27 downto 0);
        GATEHCLK        : out    vl_logic;
        SLEEPING        : out    vl_logic;
        SLEEPDEEP       : out    vl_logic;
        WAKEUP          : out    vl_logic;
        WICSENSE        : out    vl_logic_vector(33 downto 0);
        SLEEPHOLDREQn   : in     vl_logic;
        SLEEPHOLDACKn   : out    vl_logic;
        WICENREQ        : in     vl_logic;
        WICENACK        : out    vl_logic;
        CDBGPWRUPREQ    : out    vl_logic;
        CDBGPWRUPACK    : in     vl_logic;
        SE              : in     vl_logic;
        RSTBYPASS       : in     vl_logic
    );
end CORTEXM0INTEGRATION;
